The present invention relates to a cache memory which may be utilized in a microprocessor having a large capacity cache memory.
In order to enhance the performance of a microprocessor, 1) the development of micro-lithography, 2) the incorporation of a large capacity cache memory, 3) the adoption of parallel processing, and 4) the advancement of circuit technology are required. Among others, the incorporation of a large capacity cache memory is very effective in enhancing the performance of a microprocessor, since it can reduce the number of times of accessing a main memory by the microprocessor.
The cache memory, which is incorporated in a microprocessor, has three types, a direct map type, a set associative type and a full associative type.
The cache memory stores therein a high order bit of an address called a tag address and data at every block, and an address sent from a CPU is compared with the tag address. If they coincide with each other, it is called a cache hit, and, if they do not coincide with each other, it is called a cache miss. Where one comparator is used to make the addresses comparison, it is called a direct map type. If a plurality of comparators are used, it is called a set associative type, and, if a comparator is provided for every block, it is called a full associative type.
Where a cache memory is incorporated in a microprocessor (to realize high performance on a silicon chip with a limited chip area), the set associative type is usually adopted.
A microprocessor which contains a large capacity cache memory of the set associative type has been announced by Intel Corp. (L. Kohn and S. Fu, "A 1,000,000 Transistor Microprocessor", Proceedings of IEEE ISSCC '89).
In the set associative type, accessing operations are conducted in all sets. Accordingly, charging and discharging are effected on all bit lines and hence power consumption becomes great.
In a microprocessor which contains a large capacity cache memory, the integrated elements involved are very large in number and the operation speed thereof is high, which causes an increase in power consumption. As the power consumption increases, the temperature of a package and semiconductor chips rises, which causes degradation of performance characteristics and reliability of the integrated elements. As a result, it becomes necessary to employ a packaging system which uses forced cooling, etc. This eventually increases its manufacturing cost.
In the layout design of the set associative type having an odd number of sets, the number of blocks of a memory array area becomes odd. As a result, wastage of space is apt to appear in the wiring design, etc. A chip area of a large scale results in a decrease in manufacturing yield.